Various electronic design automation (EDA) tools are useful for automating the processes by which integrated circuits, multi-chip modules, boards, etc., are designed and manufactured. In particular, electronic design automation tools are useful in the design of standard integrated circuits, custom integrated circuits (e.g., ASICs), and in the design of custom configurations for programmable integrated circuits. Integrated circuits that may be programmable by a customer to produce a custom design for that customer include programmable logic devices (PLDs). Programmable logic devices refer to any integrated circuit that may be programmed to perform a desired function and include programmable logic arrays (PLAs), programmable array logic (PAL), field programmable gate arrays (FPGA), complex programmable logic devices (CPLDs), and a wide variety of other logic and memory devices that may be programmed.
As the performance requirements on FPGA designs increase (for example), it becomes increasingly difficult to distribute high-fanout signals across the chip within a single clock cycle. One of the most common high-fanout signals used in modern FPGA designs is a chip-wide asynchronous reset signal. In order to ensure proper device operation, it is important for this signal to arrive at all destination registers within the same clock cycle. This design requirement is often verified through a recovery and removal analysis performed by a timing analyzer, which is commonly implemented in many EDA tools.
For low-speed and medium-speed designs, the user has two viable options for effectively distributing an asynchronous signal: 1) use a low-skew distribution network that reaches all of, or a subset of, the target device (subsequently referred to by the terms chip-wide distribution network and distribution network, respectively) or 2) select routing resources to connect the asynchronous signal to all of its destinations (e.g., R4, R24, C4, and/or C16 resources in an Altera Stratix™ device). For sufficiently high-speed designs, neither of these options can be used to distribute the signal quickly enough to meet the timing requirement imposed on the asynchronous signal. In other words, traditional placement and routing techniques can result in failed circuit timing. Forcing the user to manually alter his or her design to satisfy this timing requirement is cumbersome and potentially sub-optimal. Therefore, a technique for distributing asynchronous signals within a logic design is desirable, such that aggressive timing requirements imposed on these signals are satisfied.